The present invention relates to an apparatus for supplying magnetic transformers and xe2x80x9cphantomxe2x80x9d power to a multi-pin connector.
As processing platforms (including personal computers and network devices) develop greater capability, the industry seeks to reduce the area needed by various components. Such platforms may be represented by a printed circuit board (PCB) and its linked components used for a personal computer, network switch, router, etc. The electrical circuitry for communicating with the platform may be implemented using a transceiver, a transformer (with associated resistors and capacitors) and a connector. Communication may be conducted through a protocol, such as the Institute for Electrical and Electronics Engineers (IEEE) standard 802.3 known as Ethernet(trademark).
The transceiver, also known as xe2x80x9cPHYxe2x80x9d or "PHgr" (for physical layer), may combine digital adaptive equalizers, phase-lock loops, line drivers, encoders, decoders and other related components. A magnetic transformer may be used to transfer electrical energy from electrically isolated circuits by magnetic fields and fluxes through its windings. The RJ-45 connector, specified under the Telecommunications Industry Association, has eight input pins to the PCB and eight output pins to a jack, with each input pin directly associated with its corresponding output pin. The jack provides a standard receiving port for twisted pair wires connected by a plug to a cable used in 10 BaseT or 100 BaseT Ethernet under IEEE 802.3X.
One method by which required board area on a PHY may be decreased involves component consolidation. The PHY handles the media access control protocols for computer interface communications. The aft region of the PCB, where a RJ-45 cable plug may be inserted into the connector, typically includes magnetic transformers for transferring electronic signals from the PHY to the connector without electrical conduction. The power conduit may also be in proximity to the connector. Typically, the magnetic transformers and power sources are shielded or separated by distance from the connector to minimize noise and electromagnetic interference (EMI).
FIG. 1 shows a schematic for a first conventional eight-pin implementation with discrete magnetics for data-exchange. A connector 10 may be coupled to a PHY 12 through a series of pins by a pair of magnetic transformers 14. The transformers 14 may be separated from the PHY 12 and the connector 10 by boundaries 16a and 16b. The PHY 12 may have a pair of receiver ports identified as Rx+ and Rxxe2x88x92 along with a complimentary pair of transmitter ports identified as Tx+ and Txxe2x88x92.
The transformers 14 may be represented by a first 1:1 winding pair 18a and a second 1:1 winding pair 18b. The windings represent a fine wire wrapped around a core for transmitting power through magnetic fields rather than by electrical conduction. The 1:1 ratio provides voltage out to equal voltage in. Each side of winding pairs may include a center tap. On the PHY or chip input side, the first and second winding pairs 18a and 18b show first and second taps 20a and 20b, respectively. On the cable output side, the first and second winding pairs 18a and 18b show third and fourth taps 20c and 20d, respectively. A center tap provides the bias voltage from the tapped side of the transformer, with an absolute value typically set to a value above ground as specified by the PHY 12. For example, if a direct current power source is applied at a center transmitter tap, the transmitter ports Tx+ and Txxe2x88x92 represent differential signals of opposite polarity fluctuating about the bias voltage. The transmitter ports provide the fluctuating voltage difference signal to be transmitted, while the center tap indicates the bias voltage value.
The PHY 12 may include a parallel circuit to the transformers 14 across the receiver ports Rx+ and Rxxe2x88x92. The receiver parallel circuit may include a first pair of 50xc2x7 resistors 22a and 22b, with a 1 nf capacitor 24a in between and terminating at a fixed potential such as ground 26. (The capacitor 24a may withstand a 50 v surge.) The PHY 12 may also include a parallel circuit to the transformers 14 across the transmitter ports Tx+ and Txxe2x88x92. The transmitter termination circuit may include a second pair of 50xcexa9 resistors 22c and 22d, with a 3.3 v voltage source 28 in between and connected to the second center tap 20b for the second winding pair 18b. 
On the cable side of the transformer 14, the fourth center tap 20d for the second winding pair 18b may be connected to a resonator or termination triplet of 75xcexa9 resistors 30a, 30b and 30c. The first two resistors may be associated with the connector 10. The third resistor 30c may be connected to a 1 nf high potential capacitor 32 that in turn may be connected to ground 26. (The high potential capacitor 32 may withstand a 2 kv surge.)
The connector 10 may include a series of pins. The RJ-45 connector includes an eight-pin configuration for input coupled to an output port 34. These may be identified as 36a for pin one, 36b for pin two, 36c for pin three, 36d for pin four, 36e for pin five, 36f for pin six, 36g for pin seven and 36h for pin eight. The first and second pins 36a and 36b may be paired to the cable side of the first winding pair 18a, thus serving as receiver connections Rx+ and Rxxe2x88x92, respectively. Alternatively, an inductor choke (not shown), used for noise suppression, may serve as a connection between the winding pair 18a and the pins 36a and 36b. The third and sixth pins 36c and 36f may be paired to the cable side of the second winding pair 18b, thus serving as transmitter connections. Tx+ and Txxe2x88x92, respectively. The fourth and fifth pins 36d and 36e may be shorted together at line 38a and paired to resistor 30a connected to the high potential capacitor 32. The seventh and eighth pins 36g and 36h may be shorted together at line 38b and paired to resistor 30b. 
Thus, pins 36a and 36b represent a receiver pair and pins 36c and 36f represent a transmitter pair. In this conventional configuration, only four of the eight pins 36a, 36b, 36c and 36f are employed for connections. The other four pins 36d, 36e, 36g and 36h remain unused. Connector input and output pins are thereby arranged as follows:
The absence of an electrical power supply to the cable side center taps prevents the connector from serving a xe2x80x9ctelephonexe2x80x9d connection or other such power requiring device, in which the power is supplied through the connection. Such a connection may include Ethernet data exchange, voice communication (with internet protocol), a power-consumption device that mimics Ethernet protocol, and measurement sensors.
Such a power source may be transferred by an in-line or xe2x80x9cphantomxe2x80x9d power source to the transformers at the center taps on the cable side. The term xe2x80x9cphantomxe2x80x9d refers to using existing wire pairs in Ethernet without additional wire or connector pin overhead. One of the signal pairs on the transformer 18b on the cable side may be biased at the direct current (DC) power voltage of the telephone. The other set of signal pairs may be biased at the DC return of the power voltage on the cable side. Since a telephone receiver on the cable side also has transformers for the Ethernet Rxxc2x1 and Txxc2x1 pairs, the DC power from the pairs may supply power to the telephone using magnetic fields and fluxes. For the Txxc2x1 and Rxxc2x1 pairs, the DC component for the bias may be considered xe2x80x9ccommon modexe2x80x9d relative to the differential signals.
FIG. 2A shows a typical pin layout between the connector and the PCB. The pins or corresponding apertures are arranged as shown in locations 36a through 36h. A ground connection 26 may be disposed in an adjacent position. FIG. 2B shows a side block diagram of the components on a PCB 40. The PHY 12, transformer 14 and connector 10 may be separated by discrete distances and connected through metal conduits in the PCB 40. The connector 10 has an aperture jack 42 through which a plug 44, connected to a twisted wire-pair cable 46, may be inserted for communicating to another device.
FIG. 3 shows a schematic for a second conventional eight-pin implementation with discrete xe2x80x9cphantomxe2x80x9d or in-line power coupled with discrete magnetics. A connector 50 may be coupled to a PHY 52 through a series of pins by a pair of transformers 54. The transformers 54 may be separated from the PHY 52 and the connector 50 by boundaries 56a and 56b. The PHY 52 may have a pair of receiver ports Rx+ and Rxxe2x88x92 along with a complimentary pair of transmitter ports Tx+ and Txxe2x88x92. The pair of transformers 54 may include center taps 20a, 20b, 20c and 20d. 
A Vdd power supply of 48v, not associated with the connector 50, may be represented by a hot lead 62a and a return lead 62b. The xe2x80x9cphantomxe2x80x9d power represents the electrical power transfer from the lead source 62a and 62b to the connector 50. The hot lead 62a may be connected to the third center tap 20c and to a 1 nf capacitor 24b and 75xcexa9 resistor 30d in series, connecting to the high potential capacitor 32 held to ground 26. The return lead 62b may be connected in parallel to the fourth center tap 20d and to a 1 nf capacitor 24c and 75xcexa9 resistor 30e in series, connecting to the high potential capacitor 32 held to ground 26. The resistors 30d and 30e may be connected to a line having a high potential capacitor 32 held to ground 26 and to a parallel pair of 75xcexa9 resistances 30a and 30b. 
The RJ-45 connector may include an eight-pin configuration for input coupled to an output port 64. The eight-pin configuration for connector 50 may be identified as 66a for pin one, 66b for pin two, 66c for pin three, 66d for pin four, 66e for pin five, 66f for pin six, 66g for pin seven and 66h for pin eight. The first and second pins 66a and 66b may be paired to the cable side of the first winding pair 18a, thus serving as receiver connections. The third and sixth pins 66c and 66f may be paired to the cable side of the second winding pair 18b, thus serving as transmitter connections. The fourth and fifth pins 66d and 66e may be shorted together by line 68a connected to resistor 30a. The seventh and eighth pins 66g and 66h may be shorted together by line 68b connected to resistor 30b. The unused pairs may be terminated with 75xcexa9 resistors and connected to the high potential capacitor 32 for surge protection. Again, only four of the eight pins 66a, 66b, 66c and 66f are employed for connections. The other four pins 66d, 66e, 66g and 66h remain unused.
A connector 10 or 50 may have a length of 0.894 inch from the PCB""s aft periphery to the fore end into the PCB 40. The discrete magnetics 12 or 52 are typically disposed an inch or more from the connector fore end as a compromise between manufacturability and magnetic isolation. A PCB 40 using discrete magnetics 12 may have the PHY interface located 1.954 inches from the connector fore edge. This region along the connector 10 represents a significant area of underutilization. Integrating the magnetics 12 into the connector 10 may reduce this PCB area consumed for magnetic shielding. The addition of xe2x80x9cphantomxe2x80x9d power increases this distance slightly to 1.996 inches.
FIG. 4 shows a schematic for an eight-pin implementation with embedded magnetics in a data-exchange circuit. A connector 70 may be coupled to a PHY 72 through a series of pins by a pair of transformers 74. In the integrated magnetics module (IMM), the transformers 74 may be embedded in the connector 70 to reduce area on a PCB 40 and/or to reduce manufacturing, inventory and installation costs.
The transformers 74 may be separated from the PHY 72 and the connector 70 by boundary 76. The PHY 72 may have a pair of receiver ports Rx+ and Rxxe2x88x92, along with a complimentary pair of transmitter ports Tx+ and Txxe2x88x92. The fourth center tap 20d for the second winding 18b may be connected to a 75xcexa9 resistor 30f that may be connected in parallel to a pair of 75xcexa9 resistors 30g and 30h and a high potential 1 nf capacitor 32 held to ground 26.
The RJ-45 connector includes an eight-pin configuration for input coupled to an output port 84. The eight-pin configuration for connector 80 may be identified as 86a for pin one, 86b for pin two, 86c for pin three, 86d for pin four, 86e for pin five, 86f for pin six, 86g for pin seven and 86h for pin eight. The first and third pins 78a and 78c may be paired to the PHY side of the first winding pair 18a, thus serving as receiver connections. The second pin 86b may be connected to the first center tap 20a on the PHY side of the first winding pair 18a. The fourth and sixth pins 86d and 86f may be paired to the PHY side of the second winding pair 18b, thus serving as transmitter connections. The fifth pin 86e may be connected to the second center tap 20b on the PHY side of the second winding pair 18b. The seventh pin 86g may be unused. The eighth pin 86h may be connected between the high potential capacitor 32 and ground 26. Unlike the discrete magnetics configurations, the PHY-to-connector interface pins for input and cable jack pins for output may not-be directly correlate in a connector with embedded magnetic transformers.
The embedding of the magnetic transformers into the connector enables the PHY 72 to be disposed from the fore edge of the magnetic integrated connector at 0.985 inch. By combining the transformer 74 and connector 70 (without xe2x80x9cphantomxe2x80x9d power), the depth is reduced by 0.969 inch, permitting either a smaller physical PCB or increased area for component installation, as well as reduced cost. However, such an implementation does not enable power to be transferred to the conductor. Consolidation of the integrated magnetics and xe2x80x9cphantomxe2x80x9d power to the connector remains an unfulfilled need in the industry.
A connector integrates a transformer and a xe2x80x9cphantomxe2x80x9d power provision, thus enabling a reduction in size along with an increase in versatility for electronic communication. The transformer may comprise a pair of magnetic windings. The power source may be connected to center taps of the magnetic transformers for providing a bias voltage to the connector.
The embedding of the magnetic transformers into the connector enables the PHY 72 to be disposed from the fore edge of the magnetic integrated connector at 0.985 inch. By combining the transformer 74 and connector 70 (without xe2x80x9cphantomxe2x80x9d power), the depth is reduced by 0.969 inch, permitting either a smaller physical PCB or increased area for component installation, as well as reduced cost. However, such an implementation does not enable power to be transferred to the connector. Consolidation of the integrated magnetics and xe2x80x9cphantomxe2x80x9d power to the connector remains an unfulfilled need in the industry.